This invention relates to circuitry and methods that enhance the operation of input buffer circuitry, and more particularly to circuitry and methods that condition signals prior to being received by the input buffer circuitry.
Input buffer circuitry is commonly used to receive signals and then transmit the received signals to other circuitry. Input buffer circuitry can be used to buffer, for example, circuitry (e.g., a programmable logic device) from input/output pins. Input buffers can be specifically designed to handle a particular type of signal (e.g., a differential signal) and can also be designed to operate according to a particular signaling standard such as Low Voltage Differential Signaling (“LVDS”). Other input buffers, such as multi-standard differential input buffers, are designed to support several signaling standards, including but not limited to, LVDS, Low Voltage Emitter Coupled Logic (“LVPECL”), LDT, and other standards used in high speed applications. Multi-standard differential input buffers are particularly useful in programmable applications because one input buffer can be used, as opposed to several, to support the desired signaling standards.
While multi-standard differential input buffers can handle two or more signaling standards, they can be susceptible to several drawbacks, especially when powered by a low voltage power supply. One such drawback is signal jitter of the output signal produced by the input buffer. Signal jitter causes a signal to appear erratic and random and it can create difficulties for other circuitry to process the signal (because the circuitry may not be able to tell if the signal is a logic LOW or HIGH). Signal jitter can be caused by prolonged time delays in signal propagation through the buffer. In general, all signals are subject to propagation delays when processed by an input buffer, but signals of certain voltages are processed much slower, resulting in prolonged propagation delays.
Sources of prolonged time delay include signals having certain ranges of common-mode voltage and relatively low differential amplitude voltage. Certain ranges of common-mode voltage can result in pronounced propagation delays because multi-standard input buffers operating with low voltage power supply voltage (e.g., at about 1.5 volts or less) may not be able to quickly process signals operating within that particular range of common-mode voltages. In addition, a relatively low differential amplitude voltage can cause propagation delays because the signal may be too weak to quickly drive the appropriate circuitry. If the voltage is too low, problems associated with inter-signal interference can occur, which can cause data-dependent jitter.
Therefore, it is an object of this invention to provide circuitry that mitigates jitter of the output signal of a multi-standard differential input buffer being supplied by a relatively low voltage power supply.